In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating T-algorithm. Through optimization at both. A Fast ACSU Architecture for Viterbi Decoder Using T-Algorithm. Jinjin He, Huaping Liu, Senior Member, IEEE, and Zhongfeng Wang*, Senior Member, IEEE. High performance ACS for Viterbi decoder using pipeline T-Algorithm .. Z. Wang, A fast ACSU architecture for Viterbi decoder using T-Algorithm, in: Proc.

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However, for TCM systems, where high-rate convolutional codes are always employed, Two steps of precomputation could achieve the iteration bound or make a big difference in terms of clock speed.

For VD in-corporated with T- algorithm, no state is guaranteed to be active at all clock cycles. The operation of searching for the best path metrics in the add-compare-select loop in T-algorithm significantly limits the clock speed. Typically a TCM system employs a high rate architectuge code, which leads to high complexity of viterbi decoder for the TCM decoder, when the decodder length of Convolutional code is also normal.

In some cases, the number of remaining metrics may slightly expand during a certain pipeline stage after addition with Bs. Subscription Login to verify subscription.

## A fast ACSU architecture for Viterbi decoder using T-algorithm

X 1 0 ………………………. Email the author Login required. Then, Bs are fed into the ACSU that recursively compute the path metrics Ps and outputs decision bits for each possible state transition. Therefore, the hardware overhead of the proposed VD is expected. At fash receiver, a soft input VD should be employed to guarantee a good coding gain.

It is essential to use T-algorithm in Viterbi decoders to prune significant portions of the trellis states to dramatically reduce power consumption.

Where q is any positive integer that is less than defoder. This algorithm is suitable for TCM systems which always employ high-rate convolutional codes. The synthesis targets to achieve the maximum clock speed for each case and the results are shown in Table III.

## Low power Viterbi decoder for Trellis coded

This is because the former decoder has a much longer critical path and the synthesis tool took extra measures to improve the clock speed. The Branch metric can be calculated by two types: From This Paper Figures, tables, and topics from this paper.

Now, we further analyze the precomputation algorithm.

Abstract The viterbi decoder which is low power with convolution encoder is show in this paper. The Basic idea of the precomputation algorithm was presented in [9]. Power reduction in VDs could be achieved by reducing the number of states, for example reduced state sequence decoding [3], M- algorithm [4] and T-algorithm [1],[5], or by over scaling the.

This information allows us to obtain the 2-step pre-computation data path. Later in the next section we will report ASIC implementation results that have not been obtained earlier. The 64 states and path metrics are labeled from 0 to Topics Discussed in This Paper.

The output of the priority encoder would be the unpurged state with the lowest index. Trellis coded modulation schemes are faet in many bandwidth efficient systems. Very Large Scale Integr. Com-pared with the conventional T-algorithm, the computational overhead of this architecture is 12 addition operations and a comparison, which is slightly more than the number obtained from the evaluation in 5.

### A fast ACSU architecture for Viterbi decoder using T-algorithm – Semantic Scholar

Suppose that we have labeled the states from 0 to Also, any kinds of low-power scheme would introduce extra hardware like decodeer purge unit shown in Fig. Hence Popt n can be calculated directly from Ps n-q in q cycles. Sri lakshmi is currently working as an assi. The minimum P becomes:.

The decrease of clock speed is inevitable since the iteration bound for VD with T -algorithm is inherently longer than that of the full-trellis VD. It is well known that viterbi decoder is dominant module for finding the overall power consumption for the TCM decoders. Therefore, a straight forward implementation of T- Algorithm will dramatically reduce the decoding speed.

Usually, the extra delay can be absorbed by an optimized architecture or circuit design.

If the target throughput is moderately high, the proposed architecture can operate at a lower supply voltage, which will lead to quadratic power reduction fir to the conventional scheme.

For clarity, we only provide the main conclusion here. Section III presents the precomputation architecture with T-algorithm.